I just wanted to summarize what I gained in terms of professional learning.
So let me open my work rough book and hmm...
............................
So let me open my work rough book and hmm...
............................
1/ Implemented Certitude work flow - A nice tool which helps improving the quality and robustness of test benches.It basically injects faults in the design and runs the regression test suite.If the suite is able to detect the fault and fail the test , then kudos -gr8 work, else there is lot more to improve in design.
2/ Learnt a basic sense of what our company is exactly involved in, what is our business strategy and about our customers and competitors
3/ Basic Difference between SHARC and Blackfin DSP.
SHARC is basically a Floating Point Processor intended for High End Audio Applications.
Blackfin whereas is a Fixed Point Processor intended for Video/Image Processing Applications
Also I came to know our TI competitor's similar products which we used in College Lab
SHARC vs TMS67
Blackfin vs TMS64
So I guess I will go through their datasheets and do a compare of how our products beat them(hopefully :) )
4/ Worked upon improving the on chip Mux testbench suite.Had issues for not properly checking the connectivity to source and few of the new features were not being exercised and some issues related to when used in GLS
Writing basic assertions:
(i) assert property
(ii) cover property
sequence--> property-->assert/cover
Implication operators : |-> and |=>
assertion clocking
5/ Started with Gate Level Simulation(GLS) from RTL level Simulation.But rather the flow transition was as follows:
(i) Zero- delay Simulation(ZDS):
In this we work with the synthesized gate level netlist but all the gates and logical elements are assumed to be ideal.That is they have no delay associated with them.Problems faced during GLS.
Possible zero delay gate oscillation detected.
netlist - synthesis optimization
Post CTS and STA netlist
cadence option : +sequence to dump simulation time step
Delta delay -- scheduling at each simulation step
(ii)GLS with assertions off
specify block
(iii)GLS with assertions on
Currently GLS is in full flow.
6/Some Jargons learnt:
Linting - syntax checker which compiler might ignore but maybe required for the synthesis tool
SDF File - Standard Delay Format File - Use to back annotate delays for GLS
GDS File - Graphic Database System File
7/ perl sleep( ) -- arg is in seconds
bsub format
bsub -q ncsim_mp -o /job%J.out(rs and super_rs)
8/ VNC and Work from home
zgrep to search in .gz file
grep -v (inverted search)
9/ Realization of why synchronous circuits required
Why Reset asserted asynchronously and de-asserted synchronously-- building deterministic cicruits
Some simple effects in combinational circuits
10/IN/OUT PAD structure
Dummy PAD--meet timing--why dummy and why not loopback from actual--PAD ringing phenomenon
11/ Tickle file syntax and use
cdnshelp :P
12/ X--propogation tool
RTL generally doesn't propogate x in state machine, it evaluates it as false.
2/ Learnt a basic sense of what our company is exactly involved in, what is our business strategy and about our customers and competitors
3/ Basic Difference between SHARC and Blackfin DSP.
SHARC is basically a Floating Point Processor intended for High End Audio Applications.
Blackfin whereas is a Fixed Point Processor intended for Video/Image Processing Applications
Also I came to know our TI competitor's similar products which we used in College Lab
SHARC vs TMS67
Blackfin vs TMS64
So I guess I will go through their datasheets and do a compare of how our products beat them(hopefully :) )
4/ Worked upon improving the on chip Mux testbench suite.Had issues for not properly checking the connectivity to source and few of the new features were not being exercised and some issues related to when used in GLS
Writing basic assertions:
(i) assert property
(ii) cover property
sequence--> property-->assert/cover
Implication operators : |-> and |=>
assertion clocking
5/ Started with Gate Level Simulation(GLS) from RTL level Simulation.But rather the flow transition was as follows:
(i) Zero- delay Simulation(ZDS):
In this we work with the synthesized gate level netlist but all the gates and logical elements are assumed to be ideal.That is they have no delay associated with them.Problems faced during GLS.
Possible zero delay gate oscillation detected.
netlist - synthesis optimization
Post CTS and STA netlist
cadence option : +sequence to dump simulation time step
Delta delay -- scheduling at each simulation step
(ii)GLS with assertions off
specify block
(iii)GLS with assertions on
Currently GLS is in full flow.
6/Some Jargons learnt:
Linting - syntax checker which compiler might ignore but maybe required for the synthesis tool
SDF File - Standard Delay Format File - Use to back annotate delays for GLS
GDS File - Graphic Database System File
7/ perl sleep( ) -- arg is in seconds
bsub format
bsub -q ncsim_mp -o /job%J.out(rs and super_rs)
8/ VNC and Work from home
zgrep to search in .gz file
grep -v (inverted search)
9/ Realization of why synchronous circuits required
Why Reset asserted asynchronously and de-asserted synchronously-- building deterministic cicruits
Some simple effects in combinational circuits
10/IN/OUT PAD structure
Dummy PAD--meet timing--why dummy and why not loopback from actual--PAD ringing phenomenon
11/ Tickle file syntax and use
cdnshelp :P
12/ X--propogation tool
RTL generally doesn't propogate x in state machine, it evaluates it as false.